1. Field of the Invention
The present invention relates to a test apparatus for a semiconductor apparatus (integrated circuit), and particularly to an IDDQ (Quiescent Vdd Supply Current) measurement technique.
2. Description of the Related Art
As a technique for assessing the quality of an LSI (Large Scale Integration), the IDDQ test is known. In the IDDQ test, a device under test (which will be abbreviate to “DUT” hereafter) is set to a quiescent state in which the electric potential and electric current are respectively set to fixed values at each of the circuit nodes of the DUT. In such a quiescent state, a quiescent power supply current (which will be abbreviated to the “IDDQ” hereafter) is measured.
In a normally manufactured CMOS (Complementary Metal Oxide Semiconductor) circuit, the drain current is substantially zero in the quiescent state in which the ON/OFF states of the transistors are respectively set to fixed states.
Specifically, only a negligibly small amount of leak current flows. In other words, in a case in which a greater amount of leak current flows, such a leak current suggests that the circuit could have malfunctioning portions or defects due to the manufacturing process. Such a malfunctioning portion due to the manufacturing process, which increases the power supply current, affects the functions of the circuit, or affects the life and reliability of the circuit.
The value of the IDDQ changes according to the electric potential states of the nodes in the circuit. That is to say, the measurement value of the IDDQ changes according to the quiescent state of the circuit. Accordingly, in a measurement in which the IDDQ is measured in a single state, it is difficult to detect the malfunctioning portions or defects.
In order to solve such a problem, a technique has been proposed in which the states of nodes in the circuit are switched according to several pattern data items supplied to the DUT, and the IDDQ is measured in each state thus switched. The states to be switched are determined by a combination of multiple data items to be supplied to the DUT. Accordingly, each state is also referred to as a “test vector”.
The IDDQ is measured for each test vector for each of multiple DUTs. The statistical value of the IDDQ is obtained for each test vector by statistically processing the measurement results. The statistical value thus obtained will also be referred to as an “expected value”. By sorting the test vectors using each of the values of the IDDQ thus obtained as a key, an IDDQ profile for the product is created. In a test in the mass production process, the quality is assessed based upon the difference between the IDDQ profile of a DUT which is to be tested and the expected IDDQ profile (which will be referred to as the “expected profile”).
[Patent Document 1]
    Japanese Patent Application Laid Open No. 2008-002900[Patent Document 2]    Japanese Patent Application Laid Open No. H08-304514
The aforementioned quality evaluation based upon the comparison result between the IDDQ profiles has the following problem. That is to say, in a case in which there is a large difference between the profile obtained by measurement and the expected profile due to variation in the process, in some cases, a product that should be assessed to be a non-defective product is assessed to be a defective product, or a product that should be assessed to be a defective product is assessed to be a non-defective product.